HuC6270
From ArchaicPixels: HuC and PCEAS Documentation
VDC. Referred to as "7UP" by NEC-HE.
Registers
$00 - MAWR - VRAM Write Address
MAWR specifies a word offset into VRAM for writing. Subsequent writes to register $02 (VWR) will store data at the offset specified by MAWR. After each write, MAWR is incremented by the amount specified in the IW bits of CR. MAWR wraps back to zero when it's value exceeds $FFFF.
The LSB and MSB of MAWR can be updated independently of each other; accessing either half directly updates the MAWR register rather than any temporary storage. This allows quick non-sequential addressing of VRAM without having to set the entire address every time.
$01 - MARR - VRAM Read Address
MARR specifies a word offset into VRAM for reading. When the MSB is written, VRAM data from the current offset is transferred into a read buffer, and then MARR is incremented by the amount specified in the IW bits of CR. For any following VRR reads, the buffered value is immediately returned and this process repeats; the buffer is loaded from data at the current offset and MARR is incremented again.
The LSB of MARR can be updated independently of the MSB. This does not cause the buffer to be loaded, only a write to the MSB will do that.
$02 - VRAM Read Buffer (VRR) / VRAM Write Latch (VWR)
Writing
When writing to VWR, the LSB is stored in a latch rather than VRAM. Any additional writes to the LSB only update the latch contents and do not affect VRAM. When the MSB is written to, the latched LSB and new MSB data are stored to VRAM at the current offset specified by MAWR. By loading the LSB with a given value and writing to the MSB repeatedly, you can fill VRAM with a constant LSB value and variable MSB value.
Reading
Reading the LSB of VRR returns the LSB of the read buffer. Reading the MSB returns the MSB of the read buffer immediately, then loads the buffer with VRAM from the current offset MARR represents and increments MARR by the value specified by the IW bits of CR. To read only the MSB of multiple words, the MSB of VRR can be repeatedly read instead of reading both the LSB and MSB.
Note: when reading from VDC addresses $0002 or $0003 when VRR is not selected, the buffer will not be reloaded nor will MARR increment when the MSB is read. The buffer contents will always return the last-loaded value but never update.
$05 - CR - Control Register
$06 - RCR - Raster Compare Register
$07 - BXR - Background X-Scroll Register
The value written to BXR is latched on each scanline, preventing mid-scanline changes to BXR. Further changes to BXR will not change the display until the next scanline is displayed. When the VDC generates synchronization signals this duration is in units of VDC scanlines, and when the VDC inputs external synchronization signals this is in units of VCE scanlines.
For example if the VDC displays multiple VDC scanlines in one VCE scanline, the same BXR value applies to all VDC scanlines until the current VCE scanline ends.
$08 - BYR - Background Y-Scroll Register
The value written to BYR is latched on each scanline, preventing mid-scanline changes to BYR. Further changes to BYR will not change the display until the next scanline is displayed. When the VDC generates synchronization signals this duration is in units of VDC scanlines, and when the VDC inputs external synchronization signals this is in units of VCE scanlines.
For example if the VDC displays multiple VDC scanlines in one VCE scanline, the same BYR value applies to all VDC scanlines until the current VCE scanline ends.
$09 - MWR - Memory Width Register
Character cycles
The fundamental unit of time observed by the VDC is the duration of one pixel clock cycle. The pixel clock is output by the VCE and can be any of the following:
- 5.36 MHz - ~186 ns per pixel
- 7.16 MHz - ~140 ns per pixel
- 10.73 MHz - ~93 ns per pixel
The VDC accesses VRAM in groups called character cycles. Each character cycle can be split into eight slots, which have a duration of one pixel clock each. The actual VRAM read or write cycle spans one or more slots, selectable in units of 1, 2, or 4 slots each.
Here's a diagram showing the number of VRAM accesses that can be made in one character cycle depending on number of slots allocated to read or write cycle:
| VRAM cycle width | Slot 1 | Slot 2 | Slot 3 | Slot 4 | Slot 5 | Slot 6 | Slot 7 | Slot 8 |
| 1 slot | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 2 slots | 1 | 2 | 3 | 4 | ||||
| 4 slots | 1 | 2 | ||||||
Within the same period of time a character cycle spans, up to 8 accesses can be done when the VRAM access cycle width is 1 slot, 4 accesses can be done when cycle width is 2 slots, and only two access can be done when the cycle width is 4 slots.
The PCE uses 100ns SRAM chips as it's video RAM, so the only situation that is problematic is using a 1-cycle dot width along with the 10.73 MHz dot clock. In this case each cycle is ~93 ns which violates the minimum access time requirements of the SRAM. In practice this does not cause any problems, however it does mean operating the memory 7% faster than it's guaranteed to work. This can be remedied by using a dot width mode with longer cycles.
VRAM dot width
The VDC will make as many sequential character cycles as the screen is wide as specified in the HDW field plus two, regardless of any horizontal scroll setting. These occur back-to-back in realtime as the display is rendered (I think there is a 1 or 2 character pipeline before any pixels are actually output). For example if the screen is 32 characters wide, 34 character cycles occur.
Bits 1,0 of MWR set the VRAM access cycle grouping, referred to as the 'VRAM dot width'. Bit 7 sets the character generator read mode when only two of four bitplanes can be read, due to insufficient VRAM access cycles available
Bits 1-0 : VRAM dot width.
| D1-D0 | Slot 1 | Slot 2 | Slot 3 | Slot 4 | Slot 5 | Slot 6 | Slot 7 | Slot 8 |
| 00b | CPU | BAT | CPU | ? | CPU | CG0 | CPU | CG1 |
| 01b | BAT | CPU | CG0 | CG1 | ||||
| 10b | BAT | CPU | CG0 | CG1 | ||||
| 11b | BAT | CG0/CG1 | ||||||
- BAT is a read from the BAT region of VRAM. (word contains palette, character name)
- CPU is a CPU access, either read or write.
- CG0 is a read from the character generator region of VRAM. (word contains bitplane 0 and 1 bytes)
- CG1 is a read from the character generator region of VRAM. (word contains bitplane 2 and 3 bytes)
The first three modes function identically. The last mode only has enough spare time in each character cycle to read CG0 or CG1, but not both. Selection of either bitplane group is done by the character generator mode bit (CM), which is bit 7 of MWR. It specifies 0= CG0 or 1= CG1. Internally, the VDC assumes the missing bitplane data is forced to zero. This means that tiles displayed when CM=0 use colors 0,1,2,3, and tiles displayed when CM=1 use colors 0,4,8,C.
Sprite dot width
During the horizontal blanking period, the VDC fetches character generator data for the sprites (up to 16) that passed y-evaluation and have their respective data buffered in the VDC's on-chip sprite storage. The bitplane data is loaded into shift registers and will be output serially during the next scanline.
The duration of the fetch period directly relates to how much horizontal blanking time is available, as defined by the HSW, HDS, HDW, and HDE registers. If the period is too short, the process is aborted. It seems the sprites that weren't loaded have their shift registers reset to zero, as previously loaded sprite data or garbage data is not shown (this needs more testing).
Much like background rendering, bits 3-2 of MWR set the character cycle allocation for sprites, referred to as the 'Sprite dot width'.
Bits 3-2 : Sprite dot width.
| D3-D2 | Slot 1 | Slot 2 | Slot 3 | Slot 4 | Slot 5 | Slot 6 | Slot 7 | Slot 8 |
| 00b | SP0 | SP1 | SP2 | SP3 | SP0 | SP1 | SP2 | SP3 |
| 01b | SP0, SP2 | SP1, SP3 | SP0, SP2 | SP1, SP3 | ||||
| 10b | SP0 | SP1 | SP2 | SP3 | ||||
| 11b | SP0/SP2 | SP1/SP3 | ||||||
- SP0-3 are sprite bitplanes 0,1,2,3
- 00b reads data for two sprites in one cycle
- 01b reads data for two sprites in two cycles (bitplanes 0,1 for sprites 1,2 in cycle, bitplanes 2,3 for sprites 1,2 in the next)
- 10b reads data for one sprite in one cycle
- 11b reads data for one sprite in one cycle, but only bitplanes 0,1 or 2,3 can be read.
Bit 0 of the pattern code field of each sprite entry specifies which bitplanes are read for a sprite dot width setting of 11b. It can be 0= SP0,SP1 or 1= SP2,SP3. The unused bitplanes are forced to zero so that the colors used out of a 16-color palette are 0,1,2,3 when SP0,SP1 are read, or 0,4,8,C when SP2,SP3 are read.
$0A - HPR - Horizontal Period Register
Bits 4-0 : Horizontal Sync Width (HSW)
Bits 14-8 : Horizontal Display Start (HDS)
HSW defines the width of the horizontal sync pulse in 8-pixel (character) units. The range is 1 to 32 characters.
HDS defines the interval after the horizontal sync pulse to the start of the horizontal display period in character units. The range is 1 to 128 characters.
When the VDC inputs external synchronization signals, the function of HSW changes. It no longer affects the width of the horizontal sync pulse. Instead, if during the processing of any VDC-generated scanline the HDE state expires prior to an external /HSYNC pulse, the number of characters as specified by HSW are taken up before the next VDC-generated scanline starts.
This distinction is important; increasing values of HSW do not displace the horizontal display area immediately following an external /HSYNC pulse, but they will for all subsequent VDC-generated scanlines before /HSYNC occurs again.
$0B - HDR - Horizontal Display Register
Bits 6-0 : Horizontal Display Width (HDW)
Bits 14-8 : Horizontal Display End (HDE)
HDW defines the width of the horizontal active display period in character units. The range is 1 to 128 characters.
HDE defines the interval following HDE to the end of the scanline, at which poinst the HSW state is entered and a horizontal sync pulse is generated. The range is 1 to 128 characters. It should be set to the remainder from the desired number of characters per scanline, minus HSW, HDS, and HDW.
$0C - VSR - Vertical Sync? Register
$0D - VDR - Vertical Display Register
$0E - VCR - Vertical Display Position End Register
Bits 7-0 : Vertical Display Position End (VCR)
VCR defines the interval following VDW to the end of the frame, at which point the VSW state is entered and a vertical sync pulse is generated. The range is 0 to 255 scanlines. It should be set to the remainder from the desired number of scanlines per frame, minus VSW, VDS, and VDW.
When the VDC inputs external synchronization signals, VCR should be set to a value equal to or larger than the number of scanlines the hardware generates from one edge of /VSYNC to the next. Otherwise the VDC will start generating another frame within the current display frame. This can be used to arbitrarily force additional VD interrupts and VRAM to SAT DMA transfers within a single VCE-defined frame.
$0F - DCR - DMA Control Register
$10 - SOUR - DMA Source Register
$11 - DESR - DMA Destination Register
$12 - LENR - DMA Length Register
$13 - SATB - SAT Source Address Register
VRAM access
Typically when loading large amounts of data into VRAM the screen is turned off for several frames. In most video hardware turning the screen off stops display related DMA and gives the CPU full access to VRAM.
The VDC handles things a bit differently. BURST mode is when the color bus outputs $0100 on VD8-VD0 (sprite palette #0, color #0), display DMA is stopped (no fetching of BAT data, background patterns, sprite patterns), and the CPU has unrestricted access to VRAM regardless of the MWR settings. BURST mode is enabled in two situations:
1. Any display state outside of VDW is considered to be in the BURST mode. A possible exception is that display DMA needs to be done on line 262 or 263 (depending on the frame height) for graphics to be displayed on scanline 0.
2. If bits 7 and 6 of CR are reset prior to VDW occurring, BURST mode is forcibly entered for the entire duration of VDW. Any changes to bits 7 and 6 have no effect until the next transition into VDW, at which point they are sampled again.
Note that this means simply turning off the background and/or sprites during VDW does *not* select BURST mode, and VRAM access is still restricted. When the background is turned off during the display, the color bus outputs $0000 on VD8-VD0 (background palette #0, color #0).
To maximize VRAM throughput, it isn't necessary to force a BURST-in-VDW display condition. The duration of VDW can just be shortened to letterbox the screen and allocate more scanlines to to the other display periods, giving more BURST time.
A MWR setting of $00 gives the CPU the largest amount of access cycles (twice per 8 pixels) which seems to be exactly equal to the amount of accesses available during BURST mode.
Pin assignments
64 41
65 +--------+ 40
| |
|. |
80 '--------+ 25
1 24
Pin Signal Description
1 /CS VDC chip select
2 /RD Write strobe
3 /WR Read strobe
4 D15 Data bus, bit 15
5 D14 Data bus, bit 14
6 D13 Data bus, bit 13
7 D12 Data bus, bit 12
8 D11 Data bus, bit 11
9 D10 Data bus, bit 10
10 D9 Data bus, bit 9
11 Ground Power supply
12 D8 Data bus, bit 8
13 D7 Data bus, bit 7
14 D6 Data bus, bit 6
15 D5 Data bus, bit 5
16 D4 Data bus, bit 4
17 D3 Data bus, bit 3
18 +5V Power supply
19 D2 Data bus, bit 2
20 D1 Data bus, bit 1
21 D0 Data bus, bit 0
22 EX8//16 Data bus width select (0= 16-bit, 1= 8-bit)
23 CK Clock input
24 /RESET Reset input
25 /VSYNC /VSYNC
26 /HSYNC /HSYNC
27 DISP Screen blanking status (0= blanked, 1= displayed)
28 SPBG Pixel bus (sprite/background indicator, 1= sprite, 0= background)
29 VD7 Pixel bus (palette value, bit 3)
30 VD6 Pixel bus (palette value, bit 2)
31 VD5 Pixel bus (palette value, bit 1)
32 +5V Power supply
33 Ground Power supply
34 VD4 Pixel bus (palette value, bit 0)
35 VD3 Pixel bus (pixel value, bit 3)
36 VD2 Pixel bus (pixel value, bit 2)
37 VD1 Pixel bus (pixel value, bit 1)
38 VD0 Pixel bus (pixel value, bit 0)
39 /MWR VRAM write strobe
40 /MRD VRAM read strobe
41 MD0a VRAM data bus, bit 0a
42 MD1a VRAM data bus, bit 1a
43 MD2a VRAM data bus, bit 2a
44 MD3a VRAM data bus, bit 3a
45 MD4a VRAM data bus, bit 4a
46 MD5a VRAM data bus, bit 5a
47 +5V Power supply
48 MD6a VRAM data bus, bit 6a
49 MD7a VRAM data bus, bit 7a
50 MD0b VRAM data bus, bit 0b
51 MD1b VRAM data bus, bit 1b
52 MD2b VRAM data bus, bit 2b
53 MD3b VRAM data bus, bit 3b
54 MD4b VRAM data bus, bit 4b
55 Ground Power supply
56 MD5b VRAM data bus, bit 5b
57 MD6b VRAM data bus, bit 6b
58 MD7b VRAM data bus, bit 7b
59 MA0 VRAM address bus, bit 0
60 MA1 VRAM address bus, bit 1
61 MA2 VRAM address bus, bit 2
62 MA3 VRAM address bus, bit 3
63 MA4 VRAM address bus, bit 4
64 MA5 VRAM address bus, bit 5
65 MA6 VRAM address bus, bit 6
66 MA7 VRAM address bus, bit 7
67 MA8 VRAM address bus, bit 8
68 MA9 VRAM address bus, bit 9
69 MA10 VRAM address bus, bit 10
70 MA11 VRAM address bus, bit 11
71 Ground Power supply
72 +5V Power supply
73 MA12 VRAM address bus, bit 12
74 MA13 VRAM address bus, bit 13
75 MA14 VRAM address bus, bit 14
76 MA15 VRAM address bus, bit 15
77 /IRQ /IRQ output to HuC6280 /IRQ1 input
78 BUSY BUSY status output
79 A0 Address bus, bit 0
80 A1 Address bus, bit 1
D15-D8 pin ordering is guessed based on D7-D0.
Not sure which half of the data bus is the MSB or the LSB, so both are D7-D0 in groups a,b
Clock input should be equal to the display pixel clock rate; e.g. 5.36 MHz.
The function of DISP, /VSYNC, /HSYNC is programmable.
The PCE uses MA15 as a chip-enable for the 64K of VRAM available in the PCE; access to addresses $8000-$FFFF means VRAM is disabled.
