Timer

From ArchaicPixels: HuC and PCEAS Documentation

The PC Engine's timer operates off of the 7.1591MHz clock. This clock is first sent into a divide-by-1024 counter, and the output of the clock divider is used to decrement the timer counter register, if the timer is enabled

When the timer counter register decrements when its value is 0, the timer counter will reload with the value contained in the timer latch, and the timer's IRQ line is activated. The timer's IRQ vector is located at logical address $FFFA.

The timer IRQ can be acknowledged(IE the timer's IRQ line made inactive again to prevent future interrupts) by reading from the IRQ mask register, or writing to the read-only IRQ status register.

Address(in I/O page)	R/W	Bits	Description
$0C00	R	Bit 7:	(Undefined, I/O data buffer D7)
		Bit 6-0:	Current timer counter value.
	W	Bit 7:	(Unused)
		Bit 6-0:	Timer latch value.
$0C01	W	Bit 7-1:	(Unused)
		Bit 0:	Timer enabled if set to 1. Writing 0, then 1, will force a reload of the timer counter from the timer latch and reset the divide-by-1024 counter.