HuC6280

From ArchaicPixels: HuC and PCEAS Documentation

The Hudson Soft HuC6280 is the 8-bit CPU of NEC's PC Engine console. It contains a customized version of a 65SC02 core, a timer, and sound generation hardware. The HuC6280 is referred to as "Dr. Pepper" or "DRP" by NEC-HE.

The 65SC02-derived-core contains enhancements such as block-memory-transfer instructions(similar instructions are seen on the 65816, in the form of MVP and MVN) and instructions to more efficiently write predefined values to the VDC.

Memory Management

The HuC6280 can address 21 bits of physical memory, but uses 16-bit logical addresses(for clarification: in "LDA $BEEF", "$BEEF" is the 16-bit logical address). Each 8kB segment of the 64kB logical addressing space has a corresponding 8-bit "MPR" register, which is used to create a 21-bit(13 lower bits of logical address + 8 bits of corresponding MPR) address sent over the bus.

PhysicalAddress = (LogicalAddress AND 0x1FFF) OR (MPR[LogicalAddress / 8192] * 8192)

Logical memory range	MPR Name
$0000-$1FFF	MPR0
$2000-$3FFF	MPR1
$4000-$5FFF	MPR2
$6000-$7FFF	MPR3
$8000-$9FFF	MPR4
$A000-$BFFF	MPR5
$C000-$DFFF	MPR6
$E000-$FFFF	MPR7

Instructions

The HuC6280 instruction set test test.

Insert opcode matrix here.

Pinout

Pin	Signal	Direction	Description
1	A5	o	Address bit 5
2	A4	o	Address bit 4
3	A3	o	Address bit 3
4	A2	o	Address bit 2
5	A1	o	Address bit 1
6	A0	o	Address bit 0
7	GND	s	Ground
8	+5V	s	Supply
9	XOUT	o	Output that follows XIN polarity, different pulse shape
10	XIN	i	21.477270 MHz clock input (OSC1)
11	/RESET	i	Reset signal input
12	RDY	i	Induce wait state while pulled low
13	SX	o	Complementary CPU clock output (7.16 or 1.79 MHz)
14	HSM	o	High Speed Mode (1= 7.16, 0= 1.78 MHz)
15	+5V	s	Supply
16	GND	s	Ground
17	LOUT	o	Audio output, left channel
18	ROUT	o	Audio output, right channel
19	VCC	s	(+5V)
20	VEE	s	(+2.5V)
21	AGND	s	(GND)
22	K0	i	Input port K ($1000.D0)
23	???	o	Unknown. Looks like a combination of SX, BSY, A0.
24	K1	i	Input port K ($1000.D1)
25	K2	i	Input port K ($1000.D2)
26	K3	i	Input port K ($1000.D3)
27	K4	i	Input port K ($1000.D4)
28	K5	i	Input port K ($1000.D5)
29	K6	i	Input port K ($1000.D6)
30	K7	i	Input port K ($1000.D7)
31	O0	o	Output port O ($1000.D0)
32	O1	o	Output port O ($1000.D1)
33	O2	o	Output port O ($1000.D2)
34	O3	o	Output port O ($1000.D3)
35	O4	o	Output port O ($1000.D4)
36	O5	o	Output port O ($1000.D5)
37	O6	o	Output port O ($1000.D6)
38	O7	o	Output port O ($1000.D7)
39	???		Always '1'
40	???		Always '1'
41	???		Always '1'
42	???		Always '1'
43	/IRQ2	i	IRQ2 interrupt input
44	/IRQ1	i	IRQ1 interrupt input
45	/NMI	i	NMI interrupt input
46	SYNC	o	Memory read type; 1= Opcode fetch, 0= Not opcode fetch
47	+5V	s	Power supply
48	GND	s	Ground
49	D0	i/o	Data bus, bit 0
50	D1	i/o	Data bus, bit 1
51	D2	i/o	Data bus, bit 2
52	D3	i/o	Data bus, bit 3
53	D4	i/o	Data bus, bit 4
54	D5	i/o	Data bus, bit 5
55	D6	i/o	Data bus, bit 6
56	D7	i/o	Data bus, bit 7
57	+5V	s	Power supply
58	GND	s	Ground
59	/CEK	o	HuC6260 /CS (@ FF:0400-0700)
60	/CE7	o	HuC6270 /CS (@ FF:0000-03FF)
61	/CER	o	Work RAM /CS (@ F8:0000-1F00)
62	/RD	o	Memory read strobe
63	/WR	o	Memory write strobe
64	A20	o	Address bus, bit 20
65	A19	o	Address bus, bit 19
66	A18	o	Address bus, bit 18
67	A17	o	Address bus, bit 17
68	A16	o	Address bus, bit 16
69	A15	o	Address bus, bit 15
70	A14	o	Address bus, bit 14
71	A13	o	Address bus, bit 13
72	A12	o	Address bus, bit 12
73	A11	o	Address bus, bit 11
74	A10	o	Address bus, bit 10
75	GND	s	Ground
76	+5V	s	Power supply
77	A9	o	Address bus, bit 9
78	A8	o	Address bus, bit 8
79	A7	o	Address bus, bit 7
80	A6	o	Address bus, bit 6

According to the patents, test terminals /EA1, /EA2, /EA3, /EAT should be present. They probably correspond to the unknown pins.

Based on information from Charles MacDonald.