HuC6261
From ArchaicPixels: HuC and PCEAS Documentation
VCE, PC-FX style.
This article is grossly incomplete, and is a Work-in-Progress.
[edit]
I/O Port Address
| Port Address | R/W | Bits | Description |
|---|
[edit]
Registers
|
[edit] $00 - Picture Mode - Halfword | ||
| Bit 1-0 | Field Configuration |
00 = 263-line frame 01 = 262-line frame 10 = Interlaced mode(262.5 per field?) 11 = Undefined |
| Bit 2 | Sychronization Source? |
0 = Internal? 1 = External? |
| Bit 3 | Pixel Dot Clock |
0 = 5.37MHz 1 = 7.16MHz |
| Bit 6 | VDC BG Palette Size |
0 = 16 entries 1 = 256 entries |
| Bit 7 | VDC SPR Palette Size |
0 = 16 entries 1 = 256 entries |
| Bit 8 | VDC BG Display |
0 = Hide VDC BG 1 = Show VDC BG |
| Bit 9 | VDC SPR Display |
0 = Hide VDC SPR 1 = Show VDC SPR |
| Bit 10 | HuC6272 BG0 Display |
0 = Hide BG0 1 = Show BG0 |
| Bit 11 | HuC6272 BG1 Display |
0 = Hide BG1 1 = Show BG1 |
| Bit 13 | HuC6272 BG2 Display |
0 = Hide BG2 1 = Show BG2 |
| Bit 14 | HuC6272 BG3 Display |
0 = Hide BG3 1 = Show BG3 |
| Bit 15 | HuC6271 Display |
0 = Hide HuC6271 output 1 = Show HuC6271 output |
|
[edit] $01 - Palette Read/Write Address - Halfword | ||
| Bit 8-0 | Palette Read/Write Address | |
|
[edit] $02 - Palette Data Read/Write Port - Halfword | ||
| Bit 15-8 | Y | |
| Bit 7-4 | U | |
| Bit 3-0 | V | |
|
[edit] $04 - VDC Palette Offset - Halfword | ||
| Bit 15-8 | BG | |
| Bit 7-0 | SPR | |
|
[edit] $05 - BMG0/BMG1 Palette Offset - Halfword | ||
| Bit 15-8 | BMG1 | |
| Bit 7-0 | BMG0 | |
|
[edit] $06 - BMG2/BMG3 Palette Offset - Halfword | ||
| Bit 15-8 | BMG3 | |
| Bit 7-0 | BMG2 | |
|
[edit] $08 - Priority 0 - Halfword | ||
|
[edit] $09 - Priority 1 - Halfword | ||
|
[edit] $0d - Fixed Color Register(CCR) - Halfword | ||
|
[edit] $0e - Cellophane Setting Register(BLE) - Halfword | ||
|
[edit] $0f - Sprite cellophane setting register(SPBL) - Halfword | ||
|
[edit] $10 - $15 - Cellophane Coefficients - Halfword | ||
| xxxxYYYYUUUUVVVV | ||
| Bit 8-11 | YYYY | |
| Bit 4-7 | UUUU | |
| Bit 0-3 | VVVV | |
