HuC6260

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VCE. Referred to as 鉄観音 - "TETSU" by NEC-HE.

Contents

Registers

$0400 - CR - Control Register

Bit 0-1DCC - Dot Clock Control W
0 = 5.37MHz
1 = 7.16MHz
2 = 10.7MHz
3 = 10.7MHz
Bit 2Frame/Field Configuration W
00 = 262-line frame
01 = 263-line frame
Bit 7Strip Colourburst W
0 = Colourburst intact
1 = Strip colourburst

$0402 - CTA - Color Table Address Register

$0404 - CTW - Color Table Write Register

$0406 - CTR - Color Table Read Register

Notes

Display artefacting

When bit 2 of $0400 is set, a flip-flop is toggled once per frame that offsets the entire frame by one pixel. I'll call this the pixel shift state. Depending on the last state of the flip-flop when bit 2 of $0400 is reset, the pixel shift state can be forced to zero or one. When enabled this completely eliminates the color fringe artefacting that is apparent for DCC settings $00-$03.

The VCE applies a 1/2 pixel shift on every even or odd scanline. The selection of even or odd scanlines is inverted on every frame, and is further inverted by the pixel shift state, however in all but 2 settings this is unnoticable.

In "C" pseudocode these work like so:

// each frame
if(dcc & 4) pixelShiftState ^= 1;

// each scanline
halfPixelShiftState = (framecount & 1) ^ (scanline & 1) ^ (pixelShiftState & 1);

Here are the results of some tests I did when the screen is filled with alternating white and black pixels on even scanlines and black and white pixels on odd scanlines. This is a worst-case test pattern for observing artefacting. Note that artefacting only affects composite and RF output, not RGB.

DCC = $00

There is a repeating pattern of pink and green columns across the display. Depending on the pixel shift state, the color order is reversed (pink,green,pink.. or green,pink,green..)

DCC = $01

The entire screen is filled with what appears as solid orange or sky blue depending on the pixel shift state.

DCC = $02

Same as $00, except for the colums are thinner due to the increased resolution.

DCC = $03

Same as $02. In this mode the half pixel shift state is not selected by the frame count anymore, just by the scanline LSB and pixel shift state. If you toggle the pixel shift state you can control if the even or odd lines have a half pixel offset. This causes a highly visible skew between pairs of scanlines due to the horizontal offset every one of two scanlines has.

DCC = $04

The rainbow pattern alternates at 30 Hz between pink and green. The result is a mostly white area.

DCC = $05

The entire screen alternates at 30 Hz between orange and sky blue. It is horrible to look at.

DCC = $06.

Same as $00, except for the colums are thinner due to the increased resolution. The columns appear to move horizontally across the screen due to their positions changing at 30 Hz.

DCC = $07

Same as $06. Because the pixel shift state is being toggled, the skew is almost not noticable.

For settings that give a 7.16 MHz dot clock ($01,$05), the pixel rate is exactly twice of the color subcarrier frequency (3.58 MHz). I think this is what causes alternating pixels to appear as a single color rather than two distinct ones.

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