Patent 5034886

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Patent for Block Transfers Instructions

Full Patent

Original Patent.

United States Patent Number: 5034886

COMPUTER SYSTEM FOR REDUCING NUMBER OF DEDICATED REGISTERS USING MEMORY STOCK AND SHARING OF ADDRESS AND GENERAL PURPOSE REGISTERS


Abstract

In a central processing unit, there are provided a address register for storing source and destination addresses and a count register for storing a length of a block data transfer. The address and count registers are wholly or partly composed of a wide use register having other functions. Therefore, the number of registers is minimized.


Field of the Invention

The invention relates to an apparatus for controlling a transfer of data, and more particularly to an apparatus for controlling a transfer of data in which block of data are transferred to minimize the number of registers.


Background of the Invention

apparatus for transferring data

A conventional comprises registers for storing source and destination addresses of memory, and a register for counting a length of a data block which is transferred between two regions of the memory.

In the apparatus for transferring data, data read from the source address of the memory are transferred to the destination address of the memory, while a length of a data block which was transferred so far is counted in the counting register. When the length becomes a predetermined length of a data block, a block transfer of data is controlled to be finished.

In the apparatus for transferring data, however, the number of registers is increased because registers for a source address, a destination address and a count of a block length are absolutely required to be provided. Especially, the disadvantage is remarkable in a case where source and destination address, and a length of a data block are designated by registers each being of 8 bits.


Summary of the Invention

Accordingly, it is an object of the invention to provide an apparatus for controlling a transfer of data in which the number of registers is minimized.

According to the invention, an apparatus for controlling a transfer of data comprises wide use register and a control means for controlling register selected from the wide use registers to store source and destination addresses and to count a length of a data block which is transferred from the source address to the destination address.


Drawings

The invention will be explained in more detail in conjunction with appended drawings wherein,

[Figure 1] is a block diagram showing an apparatus for displaying a color image to which an apparatus for controlling a transfer of data in an embodiment according to the invention is applied,

[Figure 2] is a block diagram showing an apparatus for controlling a transfer of data in the embodiment,

[Figure 3] is an explanatory diagram showing increment and decrement of source and destination addresses in an apparatus for controlling a transfer of data in the embodiment, and

[Figures 4 to 7] are flow charts explaining operation in apparatus for controlling a transfer of data in the embodiment.


Description of Preferred Embodiments

In [Figure 1], there is shown an apparatus for displaying a color image to which an apparatus for controlling a transfer of data according to the invention is applied. In the apparatus for displaying a color image, a CPU (1) performs a predetermined control in accordance with a program stored in ROM (5) so that data, arithmetical results etc. are stored into a RAM (6) temporarily. A Video Display Controller (2) is provided therein to supply a Video Color Encoder (3) with video data of a story, for instance, for a so-called television game read from a video RAM (VRAM) 7 in accordance with a control of the CPU (1) which deciphers a program for the television game stored in the ROM (5). The Video Color Encoder (3) to which the video data are supplied produces RGB analog signals obtained in accordance with color data stored therein, or produces video color signal including a luminance signal and color difference signals obtained in accordance with the color data. Further, a Programmable Sound Generator (4) is provided therein to produce analog sound signals as left and right stereo sounds in accordance with a content of the ROM (5) which is supplied through the CPU (1) thereto. The video color signal produced in the Video Color Encoder (3) is supplied through an interface 8 to a receiving circuit of a video display (9) as a composite signal, and the RGB analog signal is supplied through an interface (10) directly to a CRT of the television set which functions as an exclusive use monitor means. On the other hand, the left nd right analog sound signals are supplied through amplifiers 11a and 11b to speakers 12a and 12b to produce sounds.

[Figure 2] shows the CPU (1) and the Programmable Sound Generator (4) as encircled by a dotted line in [Figure 1]. The CPU (1) in which an apparatus for controlling a transfer of data in the embodiment is included and comprises:

  • an instruction register (20)
  • an instruction decoder (21)
  • a bus interface register (22)
  • an Arithmetic Logic Unit (ALU) (23)
  • a set of registers (24)
  • a Mapping Register (25)
  • a chip enable decoder (26)
  • a timing and control unit (27)
  • an input and output port (28)
  • a Timer (29)
  • an interrupt request register (30)
  • an interrupt disable register (31)
  • and so on.

These units will be explained as follows. [list=1] [*] instruction register (20) The instruction register (20) is loaded with an instruction code at an instruction fetch cycle.

[*] instruction decoder (21) The instruction decoder (21) performs a sequential operation determined in accordance with an output of the instruction register (20), an interruption input from a peripheral circuit or a reset input, and further performs a control of a divergence command changing a flow of a program in accordance with informations of a status register described later.

[*] bus interface register (22) The bus interface register (22) controls a transfer of data among a B-bus (32), a U-bus (33) and an external bus D0 to D7. The ALU (23) and the set of registers (24) are connected by the B-bus (22), and the U-bus (33) is connected to internal periphery circuits. Further, a L-bus (34) for transferring lower 8 bits of a logical address and a H-bus (35) for transferring upper 8 bits of the logical address are provided. A logical address low register 48 is connected to the L-bus (34), and a logical address high register 49 is connected to the H-bus (35).

[*] ALU (23) The ALU (23) is provided with an A register (36) and a B register (37), and performs all of arithmetic and logic operation. The A and B registers 36 and 37 are loaded with one or two data so that an arithmetic operation is performed in accordance with a control signal of the instruction decoder (21) to supply one of the B-bus (32), L-bus (34) and H-bus (35) with a result of the arithmetic operation.

[*] set of registers (24) The set of registers (24) comprises following 10 registers each being of 8 bits.

[list=1] [*] Accumulator (38)

The Accumulator (38) is a wide use register which plays the most important role in an arithmetic and logic operation to be conducted when a memory arithmetic flag T of a status register described later is 0. Data thereof is supplied to an input of the ALU (23), and a result of the arithmetic is stored therein. The Accumulator (38) is also used for a transfer of data between memories and between a memory and a peripheral circuit, and for a count of a data block length when a block transfer of data is performed. A lower data of the length are stored therein after data stored therein at the very moment are evacuated into a stack region of the RAM (6).

[*] X and Y registers (39 and 40)

The X and Y registers (39 and 40) are wide use registers which are mainly used for an index addressing. The X register (39) is used for a designation of an address on page 0 of a memory which is a destination of an arithmetic operation, and for a storage of lower data of a source address after data stored therein at the very moment are evacuated into a stack region of the RAM (6) when a block transfer of data is performed. On the other hand, the Y register (40) stores lower data of a destination address after data stored therein at the very moment are evacuated into a stack region of the RAM (6) when a block transfer of data is performed.

[*] Program Counters (41 and 42)

An up counter of 16 bits is composed of the Program Counter (41) of upper 8 bits and the Program Counter (42) of lower 8 bits. The up counter is automatically incremented in accordance with the conduct of a command to designate an address of a command or operand to be next conducted. Contents of the Program Counters (41 and 42) are evacuated into a stack region of the RAM (6) in a case where a command of subroutine is conducted, and an interrupt is produced, or after an interruption command of a software is conducted.

[*] Stack Pointer (43)

The Stack Pointer (43) designates lower 8 bits of the highest address on a stack region of the RAM (6), and is decremented after the pushing of data into the stack region and incremented before the pulling of the data from the stack region. For instance, 256 bytes of addresses 0x2100 to 0x21FF are allocated to the stack region in a logical address.

[*] source high register (45), destination high register (46), and length high register (47)

These registers function in case of a command of a block transfer. The source high register (45) provides an upper byte of a source address to designate the source address together with a content of the X register (39). The destination high register (46) provides an upper byte of a destination address to designate the destination address together with a content of the Y register (40). The length high register (47) provides lower 8 bits for a down counter together with upper 8 bits which are a content of the Accumulator (38) so that a length of a block transfer is counted by a byte unit. [/list] [*] Mapping Register (25) The Mapping Register (25) is composed of 8 registers each being of 8 bits to convert a logical address of 16 bits to a physical address of 21 bits, and is selected by upper 3 bits of the H-bus (35).

[*] chip enable decoder (26) The chip enable decoder (26) provides chip enable outputs for following peripheral circuits by decoding upper 11 bits of a physical address.

[list=1] [*] a chip enable for the RAM (6)...CER [*] a chip enable for the Video Display Controller (2)...CE7 [*] a chip enable for the Video Color Encoder (3)...CEK [*] a chip enable for the Programmable Sound Generator (4)...CEP [*] a chip enable for the Timer (29)...CET [*] a chip enable for the input and output port...CE10 [*] a chip enable for the interrupt request register (30) and the interrupt disable register (31)...CECG [/list]

[*] timing and control unit (27) The timing and control unit (27) is connected to the following terminals.

[list=1] [*] RD terminal A read timing signal is supplied through the RD terminal at a reading cycle.

[*] WR terminal A write timing signal is supplied through the WR terminal at a writing cycle.

[*] SYNC terminal A synchronous signal of High is supplied through the SYNC terminal at an instruction fetch cycle, that of Low is supplied therethrough at a system reset timing.

[*] NMI terminal A non-maskable interruption is produced when NMI input signal is supplied through the NMI terminal. A sub-routine call is conducted by reading lower address from the logical address 0xFFFC and upper address from the logical address 0xFFFD when a command which is conducted in a program is completed.

[*] IRQ1 and IRQ2 terminals

A sub-routine call is conducted by reading lower address from the logical address 0xFFF8 and upper address from the logical address 0xFFF9 when IRQ1 input becomes Low in a case where a corresponding bit in the interrupt disable register (31) is 0, and a corresponding bit in the Status Register (44) is 0. At this time, the corresponding bit is set in the Status Register (44), and other corresponding bits are reset therein.

A sub-routine call is conducted by reading lower address from the logical address 0xFFF6 and upper address from the logical address 0xFFF7 when IRQ2 input becomes Low in a case where a corresponding bit in the interrupt disable register (31) is 0, and a corresponding bit in the Status Register (44) is 0. At this time, the corresponding bit is set in the Status Register (44), and other corresponding bits are reset therein.

[*] RESET terminal A program is started by reading lower address from the physical address 0x00001FFE and upper address from the physical address 0x00001FFF when a RESET input becomes Low.

[*] RDY terminal The CPU (1) is started to operate when a RDY input is changed from Low to High.

[*] SX terminal A complementary signal of a system clock signal is supplied through the SX terminal.

[*] OSCI terminal An external clock signal is input through the OSCI terminal.

[*] EA1 to EA3 terminals These are input terminals for a test of the CPU (1).

[*] HSM terminal A speed mode signal of High is supplied through the HSM terminal in case of a high speed mode of 21.477270 MHz/3, and that of Low is supplied therethrough in case of a low speed mode of 21.477270 MHz/12. [/list] [*] input and output port (28) The input and output port (28) is connected to following terminals.

[list=1] [*] K0 to K7 terminals The terminals are input ports from which data are written in accordance with the conduct of a reading cycle in regard to the physical addresses 0x001FF000 to 0x001FF3FF.

[*] 00 to 07 terminals The terminals are output ports with latches to which data are supplied in accordance with the conduct of a writing cycle in regard to the physical addresses 0x001FF000 to 0x001FF3FF. [/list]

[*] Timer (29)

The Timer (29) is connected to a test input terminal EAT for the CPU (1) and provides a timer signal through the U-bus thereto.

[*] interrupt request register (30) The interrupt request register (30) is of 8 bits among which 5 bits are not used, while the remaining 2 bits are 1 to make the IRQ1 and IRQ2 terminals Low and the remaining 1 bit is 1 to produce a timer interrupt signal. The interrupt request register (30) is only used for read.

[*] interrupt disable register (31) The interrupt disable register (31) is of 8 bits among which 5 bits are not used, while the remaining 2 bits are 1 to make an interrupt request of the IRQ1 and IRQ2 terminals disable, and the remaining one is 1 to make an interrupt request disable in accordance with the timer interrupt signal. [/list]

In operation, when one of commands TII, TIN, TIA, TAI and TDD for a block transfer of data as shown in [Figure 3] is produced, contents of the Accumulator (38), the X register (39) and the Y register (40) are evacuated into a stack region of the RAM (6). Thereafter, the Accumulator (38) stores lower data of a length for the block transfer, the X register (39) stores lower data of a source address, and the Y register (40) stores lower data of a destination address. Simultaneously, the source high register (45) stores upper data of the source address, the destination high register (46) stores upper data of the destination address, and the length high register (47) stores upper data of the length for the block transfer. Thus, corresponding registers are loaded with the source address, the destination address, and the block length respectively. At the present stage, the memory arithmetic flag T of the Status Register (44) is 0. Next, the aforementioned block transfer commands TII, TIN, TIA, TAI and TDD will be explained in conjunction with [Figure 3] to 7.

[list=1] [*] TII ([Figures 3 and 4]) In accordance with the command TII, data are transferred in a block of a predetermined length such that the source and destination addresses are automatically incremented. At first, contents of the Accumulator (38), the X register (39), and Y register (40) are evacuated into the stack region MS as shown in [Figure 4] (block 410) by MS ← Y, MS ← A and MS ← X, and the Stack Pointer (43) is decremented after the pushing of data into the stack region MS as shown in [Figure 4] (block 410) by S ← S - 1. Thus, the block transfer of data is performed from a memory MSS designated by the source high and X registers (45 and 39) to a memory MDD designated by the destination high and Y registers (46 and 40) as shown in [Figure 4] (block 420) by MDD ← MSS. During this transferring stage,the source and destination addresses are incremented by each transfer of one byte as shown in [Figure 4] (block 420) by SL ← SL + 1, SH ← SH + C, DL ← DL + 1, DH ← DH + C. When contents of the length high register (47) and the Accumulator (38) for the length counter becomes 0, that is, Low is 0, in accordance with a down count as shown in [Figure 4] (block 430, block 420) by LL ← LL - 1, LH ← LH - C, the block transfer is completed. At this moment, data which have been evacuated in the stack region MS are restored in the Accumulator (38), the X register (39), and the Y register (40) as shown in [Figure 4] (block 440) by X ← MS, A ← MS and Y ← MS, and the Stack Pointer (S) is incremented as shown in [Figure 4] (block 440) by S ← S + 1.

[*] TIN ([Figures 3 and 5]) Although like operating steps are indicated by like expressions between [Figures 4 and 5], the difference is that an address of a source memory is incremented by each transfer of one byte, while an address of a destination address is fixed (block 510).

[*] TIA ([Figures 3 and 6]) Although an address of a source memory is incremented by each transfer of one byte, an address of a destination memory is incremented and decremented alternately by each transfer of one byte (blocks 610 and 620).

[*] TAI ([Figure 3]) Although a flow chart is not shown for the embodiment, an address of a source memory is incremented and decremented alternately by each transfer of one byte, an address of a destination memory is only incremented.

[*] TDD ([Figures 3 and 7]) Both addresses of a source memory and a destination memory are decremented by each transfer of one byte (block 710). [/list] In the embodiments in which increment and decrement of an address are alternately performed, it becomes easy to set up an interface between the apparatus of the invention and a peripheral integrated circuit.


Claims

Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

What is claimed is:

  1. An apparatus for controlling transfer of data comprising:

    • a source address register for storing half the number of bits of a source address of a memory from which said data are read.
    • a destination address register for storing half the number of bits of a destination address of a memory into which said data are read.
    • a count register for storing half the number of bits of data corresponding to the block length of data which is transferred from said source address to said destination address.
    • a central processing unit including first to third registers each storing predetermined data for execution of a programmed process in said central processing unit.

    said central processing unit further including means for transferring said predetermined data from said first to third registers to a stack region of memory, and storing the remaining number of bits of said source address, destination address and data block length, respectively, in the said first to third registers for performing a block data transfer.

  2. An apparatus for controlling transfer of data, according to claim 1, wherein said source address register, said destination address register and said counter register store upper data and said first to third registers store lower data.
  3. An apparatus for controlling transfer of data, according to claim 1, wherein said means for transferring said predetermined data comprises status pointer means for designating lower bits of the highest address on said stack region and status register means.