HuC6260

The HuC6260

The HuC6260 is the Video Color Encoder (VCE), Referred to as 鉄観音 - "TETSU" by NEC-HE.

The VCE basically supplies the picture on your television.

It is connected to the HuC6280 and the HuC6270. The HuC6280 provides palettes and can modify a few settings while the HuC6270 provides a data stream to which it applies the palettes.

Notes

• all mentions of "dot" have been replaced with "pixel" (DCC is now PCC)
• all registers are 16 bit.

Interface

Needs verification

Pins	Function	Input/Output	Connection
A0 - A2	Register Selection	Input	A0 - A2 from CPU
RD	Activate read from register	Input	RD from CPU
WR	Activate write to register	Input	WR from CPU
D0 - D7	Data bus for registers	Input / Output	D0 - D7 from CPU
VD0 - VD8		Input / Output	VD0 - VD7, SPBG from VDC
HSYNC	Horizontal Synchronization	Input / Output	HSYNC from VDC
VSYNC	Vertical Synchronization	Input / Output	VSYNC from VDC

Registers

$0400 - CR - Control Register

Write only register.

Bit(s)	Description	Values
0 - 1	PCC - Pixel Clock Control	00 = 5.3693175 MHz 01 = 7.15909 MHz 10 = 10.738635 MHz 11 = 10.738635 MHz
2	Frame/Field Configuration	0 = 262-line frame 1 = 263-line frame
3 - 6	???	???
7	Strip Colorburst	0 = Colorburst intact 1 = Strip colorburst
8 - 15	(unused)

$0402 - CTA - Color Table Address Register

Write only register.

Bit(s)	Description	Values
0 - 8	index for the color table	0 to 511
9 - 15	(unused)

Note: This register is auto-incremented after each access to the color data register.

$0404 - CTW - Color Table Write Register / CTR - Color Table Read Register

Write/Read register.

Access (read/write) to this register causes CTA register to increment.

Bit(s)	Description
0 - 2	Blue
3 - 5	Red
6 - 8	Green
9 - 15	(unused)

Notes

Display artifact
When bit 2 of $0400 is set, a flip-flop is toggled once per frame that offsets the entire frame by one pixel. I'll call this the pixel shift state. Depending on the last state of the flip-flop when bit 2 of $0400 is reset, the pixel shift state can be forced to zero or one. When enabled this completely eliminates the color fringe artifact (chromatic aberration) that is apparent for PCC settings $00-$03.

The VCE applies a 1/2 pixel shift on every even or odd scanline. The selection of even or odd scanlines is inverted on every frame, and is further inverted by the pixel shift state, however in all but 2 settings this is unnoticable.

In "C" pseudocode these work like so:

  //each frame 
  if(dcc & 4) pixelShiftState ^= 1;
  //each scanline
  halfPixelShiftState = (framecount & 1) ^ (scanline & 1) ^ (pixelShiftState & 1);

Here are the results of some tests I did when the screen is filled with alternating white and black pixels on even scanlines and black and white pixels on odd scanlines.

This is a worst-case test pattern for observing artifacting (note that artifacting only affects composite and RF output not RGB)

PCC	Effect
$00	There is a repeating pattern of pink and green columns across the display. Depending on the pixel shift state, the color order is reversed (pink, green, pink.. or green, pink, green...).
$01	The entire screen is filled with what appears as solid orange or sky blue depending on the pixel shift state.
$02	Same as $00, except for the columns are thinner due to the increased resolution.
$03	Same as $02. In this mode the half pixel shift state is not selected by the frame count anymore, just by the scanline LSB and pixel shift state. If you toggle the pixel shift state you can control if the even or odd lines have a half pixel offset. This causes a highly visible skew between pairs of scanlines due to the horizontal offset every one of two scanlines has.
$04	The rainbow pattern alternates at 30 Hz between pink and green. The result is a mostly white area.
$05	The entire screen alternates at 30 Hz between orange and sky blue. It is horrible to look at.
$06	Same as $00, except for the columns are thinner due to the increased resolution. The columns appear to move horizontally across the screen due to their positions changing at 30 Hz.
$07	Same as $06. Because the pixel shift state is being toggled, the skew is almost not noticeable.

For settings that give a 7.15909 MHz pixel clock ($01 and $05), the pixel rate is exactly twice of the color subcarrier frequency (3.579545 MHz). I think this is what causing alternating pixels to appear as a single color rather than two distinct ones.

Pin assignments

HuC6260 Pinout

HuC6260 Circuit

Pin	Signal	Direction	Description
1		N/A	Not Connected
2	XIN	in	21.477270 MHz clock input (OSC)
3	GND	s	Ground
4	D8	in / out	Data bus, bit 8 / Not Connected!
5	D7	in / out	Data bus, bit 7
6	D6	in / out	Data bus, bit 6
7	D5	in / out	Data bus, bit 5
8	D4	in / out	Data bus, bit 4
9	D3	in / out	Data bus, bit 3
10	D2	in / out	Data bus, bit 2
11	D1	in / out	Data bus, bit 1
12	D0	in / out	Data bus, bit 0
13		N/A	Not Connected
14		N/A	Not Connected
15		N/A	Not Connected
16		N/A	Not Connected
17	BRT-	out
18	BRTC	out
19		N/A	Not Connected
20	BURS
21		N/A	Not Connected
22	BRT+	out
23	B-Y-	out
24	B-YC	out
25		N/A	Not Connected
26	B-Y	out
27		N/A	Not Connected
28	B-Y+	out
29		N/A	Not Connected
30	R-Y+	out
31	R-YC	out
32		N/A	Not Connected
33	R-Y	out
34		N/A	Not Connected
35	R-Y+	out
36		N/A	Not Connected
37	Y-	out
38	YC	out
39		N/A	Not Connected
40	Y	out
41		N/A	Not Connected
42	Y+	out
43	SYN-	out
44	SYNC	out
45	SYN+	out
46	RGB-	out
47	VIDEO G	out
48		N/A	Not Connected
49	VIDEO R	out
50		N/A	Not Connected
51	VIDEO R	out
52	RGB+	out
53		N/A	Not Connected
54		N/A	Not Connected
55		N/A	Not Connected
56		N/A	Not Connected
57		N/A	Not Connected
58		N/A	Not Connected
59		N/A	Not Connected
60		N/A	Not Connected
61	SEL
62	VD0	in / out
63	VD1	in / out
64	VD2	in / out
65	VD3	in / out
66	VD4	in / out
67	VD5	in / out
68	VD6	in / out
69	VD7	in / out
70	VD8	in / out
71	HSYN	in / out
72	VSYN	in / out
73	CK	out
74	A0	in
75	A1	in
76	A2	in
77	WR	in
78	CS	in
79		N/A	Not Connected
80	8/16	in

Patents

Patent for VCE

Patent for VCE/VDC

Patent for Video Output

Full Patent

Original Patent

United States Patent Number: 5059955
APPARATUS FOR PRODUCING VIDEO SIGNALS




In [Figure 1], there is shown a color image displaying apparatus to which an apparatus for producing video signals is applied. The color image displaying apparatus comprises a CPU (1) for controlling the whole system, a ROM (2) for storing programs by which the whole system is controlled, a RAM (3) for storing data and calculation results temporarily, a Video Color Encoder (4) which is an apparatus for producing video signals in the invention and which produces output signals A of analog RGB signals and B of a composite signal, a Video Display Controller (5) for controlling a supply of video data to the Video Color Encoder (4), a VRAM (6) for storing video data to be supplied to the Video Color Encoder (4), and a video display (9) for displaying a color image in accordance with the analog RGB signals or the composite signal.


 
  
[Figure 1] is a block diagram showing a color image displaying apparatus to which an apparatus for producing video signals in an embodiment according to the invention is applied.



[Figure 2] shows the Video Color Encoder (4) which is an apparatus for producing video signals in the embodiment according to the invention. In the Video Color Encoder (4), a 8/16 bit data bus interface (23) and an Address Register (24) are provided to be connected through a CPU data bus (21) of 9 bits D0 to D8 to the CPU (1), and an address selector (25) is provided to be connected through a VDC data bus (22) of 9 bits VD0 to VD8 to the Video Display Controller (5). The 8/16 bit data bus interface (23) has a function that the Video Color Encoder (4) is connected to the CPU (1) of 8 bits or 16 bits, and the address selector (25) selects one data from data in the Address Register (24) and data on the VDC data bus (22) as an address signal. A color table RAM (26) is connected to the 8/16 bit data bus interface (23), and a data latch circuit (27) having three outputs for R, G and B color data is connected to the color table RAM (26) so that color data read from the color table RAM (26) are latched in the data latch circuit (27). The three outputs of the data latch circuit (27) are connected to digital to analog converters (28, 29 and 30) for R, G and B color data and to a matrix ROM (31) having a signal conversion matrix therein in which color data are converted to a luminance signal Y, and color difference signals R-Y and B-Y. The 8/16 bit data bus interface (23), the Address Register (24), the address selector (25), the color table RAM (26), and the data latch circuit (27) are controlled together with a synchronous signal producing circuit (33) by a control circuit (32) having inputs of a 8/16 bit selection signal EX 8/16, a chip selection signal (CS), a writing signal (WR), a reading signal (RD), an output control signal (CESEL) etc. The synchronous signal producing circuit (33) receives an oscillation signal of a sinusoidal wave having a frequency of, for instance, 21.47727 MHz from an oscillation circuit (33A) and produces horizontal and vertical synchronous signals (HSYNC and VSYNC), pixel clock signals (CK), color subcarriers etc. The R, G and B digital to analog converters (28, 29 and 30) are connected to an analog RGB signal output circuit (41A) to which a synchronous signal composite circuit (34) is also connected. Outputs of the matrix ROM (31) are connected to digital to analog converters (35, 36 and 37) for the luminance signal Y, and the color difference signals R-Y and B-Y. The R-Y and B-Y digital to analog converters (36 and 37) are connected to modulators (38 and 39) in which the two color subcarriers of the same frequency and different phases by ninety degrees supplied from the synchronous signal producing circuit (33) are modulated by the color difference signals R-Y and B-Y, respectively, so that color carrier signals are produced therein. One of the color subcarriers is also supplied to a burst circuit (40) in which a burst signal is produced by inserting the color subcarrier of 8 or nine cycles at a period of back porch of the horizontal synchronous signal. In the Y digital to analog converter (35), the luminance signal is combined with the synchronous signals. The Y digital to analog converter (35), the modulators (38 and 39), and the burst circuit (40) are connected to a composite signal output circuit (41B).


 
  
[Figure 2] is a block diagram showing an apparatus for producing video signals in the embodiment



In [Figure 3], there are explained a Control Register (CR), a Color Table Address register (CTA), a Color Table data Write register (CTW), and a Color Table data Read register (CTR) included in the control circuit (32). These registers are enabled with the chip selection signal (CS) 0 and one of them is selected with a content of the address A1 and A2 as follows.
In regard to a bit width selection, a bit width of 16 bits is selected when the signal EX 8/16 is 0, while a bit width of 8 bits is selected when the signal EX 8/16 is 1. In a case where the 8 bit width is selected, transferred data are of a lower byte for a register when the address A0 is 0, and transferred data are of an upper byte for a register when the address A0 is 1.
The Control Register (CR) includes frequency dividing data PCC in lower 8 bits.


 
  
[Figure 3] is an explanatory diagram explaining registers used in an apparatus for producing video signals in the embodiment



In [Figure 4], there is explained a relation between an oscillation frequency of a sinusoidal wave in the oscillation circuit (31A) and a square wave pixel clock frequency (CK) wherein the dividing ratio is four when the content PCC is 0x00, and the dividing ratio is three when the content PCC is 0x01. In [Figure 4], the expression "fsc " indicates a frequency of a color subcarrier so that the expression "6fsc " means that a sinusoidal wave having a frequency of six times that of the color subcarrier is supplied to the synchronous signal producing circuit (33). Thus, the frequency dividing ratio of the synchronous signal producing circuit (33) is controlled by the Control Register (CR).
The Color Table Address register (CTA) includes a starting address CTA at lower 9 bits. The starting address is an address for the color table RAM (26) from which data transferred from the CPU (1) are started to be written into the color table RAM (26). When an address is set in the Address Register (24), the address is automatically incremented by one each time when data are read or written.
The Color Table data Write register (CTW) and the Color Table data Read register (CTR) include 3 bit color data for R, G and B at lower 9 bits respectively, and are used for a transfer of data between the CPU (1) and the color table RAM (26).


 
  
[Figure 4] is an explanatory diagram explaining a dividing ratio of an oscillation frequency



[Figure 5] shows video data VD0 to VD8 supplied from the Video Display Controller (5). The most significant bit VD8 defines a kind of data, that is, when the bit VD8 is 0, the data VD0 to VD7 are of a background, and when the bit VD8 is 1, the data VD0 to VD7 are of a sprite. In the data VD0 to VD7, the upper 4 bits VD4 to VD7 are of an address signal for addressing area color (a designation of a block), and the lower 4 bits VD0 to VD3 are of an address signal for addressing one color data in a block.


 
  
[Figure 5] is an explanatory diagram explaining video data



[Figures 6A and 6B] show the color table RAM (26) in which a region A includes color data for a background, and a region B includes color data for sprites. The regions A and B includes 16 blocks O to F each including 16 addresses 0 to F. The color table RAM (26) includes a memory region for color data R, G and B each being of 3 bits. As apparent from the above, the regions A and B have 256 addresses respectively so that 512 colors can be displayed.


 
  
[Figures 6A and 6B] are explanatory diagrams showing a color table RAM in an apparatus for producing video signals in the embodiment



[Figure 7] shows the matrix ROM (31) which stores luminance signals Y, color difference signals B-Y and R-Y at addresses of R, G an B color signals read from the color table RAM (26) to be latched in the latch circuit (27). For instance, when the color data are that G is 000, R is 000, and B is 010, the color difference signals B-Y and R-Y are 0x14 and 0x0F, and the luminance signal is 0x01.


 
  
[Figure 7] is an explanatory diagram showing a matrix ROM in an apparatus for producing video signal in the embodiment



[Figure 8A] shows the address selector (25), the color table RAM (26) and the matrix ROM (31) as shown in [Figure 2]. A first flip-flop (25a) is provided to function as a latch circuit at a front stage of the address selector (25), and second and third flip-flops (27a and 27b) are provided as the latch circuit (27) in [Figure 2] at a rear stage of the color table RAM (26). The operation of the first to third flip-flops (25a, 27a and 27b) are controlled with timings of pixel clocks (CK), provided tat the third flip-flop (27b) is controlled with pixel clocks (CK) passed through an AND circuit (42) having two inputs connected to a pixel clock terminal and a delay circuit (43). The delay circuit (43) produces a signal 0 when the chip selection signal (CS) is 0, and a signal 1 when a predetermined time T is elapsed after the chip selection signal (CS) becomes 1 from 0. A fourth flip-flop is connected to an output of the matrix ROM (31).
In operation, color data are first written into the color table RAM (26) through a process in which the Color Table Address register (CTA) is addressed with address signals A1 and A2 of 1 and 0 so that a starting address CTA of the color table RAM (26) is set therein. In a case where the 16 bit width is selected, the starting address is set by one time. While, in a case where the 8 bit width is selected, the starting address is set in such a manner that a lower byte is first set therein and an upper byte is then set therein. Next, color data are written into the color table RAM (26) at the address in such a manner that the color data are written thereinto by one time in case of 16 bit width, while a lower byte thereof and then an upper byte thereof are written thereinto in case of 8 bit width. Then, an address of the color table RAM (26) is automatically incremented so that color data are successively written thereinto.
When video data as shown in [Figure 5] are transferred through the VDC data bus (22) from the Video Display Controller (5) to the Video Color Encoder (4), the address selector (25) selects the transferred video data to decide an address of the color table RAM (26) as shown in [Figures 6A and 6B] so that color data of R, G and B are read therefrom to be latched in the latch circuit (27) in accordance with the pixel clock (CK). At this moment, one of regions A and B is selected dependent on a content of the VD8 bit as described before, and a predetermined block is selected in the selected region A or B dependent on a content of the VD4 to VD7 bits. In the selected block, a predetermined address is accessed dependent on a content of the VD0 to VD3 bits. When color data are latched in the latch circuit (27), analog RGB signals or a composite signal can be supplied from the analog RGB signal output circuit (41A) or the composite signal output circuit (41B) through the interface 7 or 8 to the video display (9).


Output of analog RGB signals
When the frequency dividing ratio PCC of the Control Register (CR) is set to be 0x01, the frequency dividing ratio is three as shown in [Figure 4]. Digital RGB color data in the latch circuit (27) are converted in the R, G and B digital to analog converters (28, 29 and 30) to produce analog RGB signals. Simultaneously, horizontal and vertical synchronous signals HSYNC and VSYNC supplied from the synchronous signal producing circuit (33) are combined in the synchronous signal composite circuit (34) to produce a composite synchronous signal. Then, these analog RGB and composite synchronous signals are supplied from the analog RGB signal output circuit (41A) directly to the video display (9) or to an exclusively used monitor means (not shown). The analog RGB signals thus supplied thereto are of a video band of 7 MHz. On the contrary, the video band will be 5 MHz, if the frequency dividing ratio is set to four.

Output of a composite signal
When the dividing ratio PCC of the Control Register (CR) is set to be 0x00, the dividing ratio is four. A luminance signal Y and color difference signals R-Y and B-Y are supplied from the matrix ROM in accordance with R, G and B color data latched in the latch circuit (27), and then converted in the digital to analog converters 35, 36 and 37 to analog signals. At this moment, the luminance signals Y are combined with the synchronous signals from the synchronous signal producing circuit (33). On the other hand, color carriers are obtained from the balanced modulation of color subcarriers having the same frequency and different phases by ninety degrees, which are supplied from the synchronous signal producing circuit (33) in accordance with the color difference signals R-Y and B-Y. Further, a burst signal is obtained from the insertion of the color subcarrier of 8 or nine cycles into a back porch period of the horizontal synchronous signal in the burst signal producing circuit 40. These signals thus obtained are combined in the composite signal output circuit (41B) to produce a composite signal which is then supplied through the interface (8) to a receiving circuit of the video display (9) to be displayed on the video display thereof. The composite signal is of a video band of 5 MHz and is based on a system of NTSC. As a matter of course, the video band may be 7 MHz as described before.
Next, a timing at which RGB color data are latched in the latch circuit (27) with the pixel clock (CK) will be described in more detail in conjunction with [Figures 8A and 8B].
When video data VD0 to VD8 are transferred from the Video Display Controller (5) to the Video Color Encoder (4), the video data are latched in the first flip-flop (25a), and the color table RAM (26) is addressed with an address signal of the video data VD0 to VD8 so that RGB color data are read from the color table RAM (26) to be latched in the second flip-flop (27a). When a first bit of the second flip-flop (27a) is latched in the third flip-flop (27b), it is assumed that the chip selection signal (CS) becomes 0 for the purpose that data are written into the color table RAM (26) by the CPU (1). As a result, an output of the delay circuit (43) becomes 0 to result in no output of the pixel clock (CK) from the AND circuit (42). Therefore, a second bit and signals following after the second bit in the second flip-flop (27a) are prevented from being latched in the third flip-flop (27b). Thereafter, when the chip selection signal (CS) becomes " 1", the delay circuit (43) times a predetermined time T, and when the time T is elapsed, an output of the delay circuit (43) becomes 1. Accordingly, the pixel clock (CK) is again supplied to the third flip-flop (27b) so that an 8 bit and signals following after the 8 bit in the second flip-flop (27a) are latched in the third flip-flop (27b) to be supplied to a following stage as digital RGB signals. At this moment, an output of RGB color data is prohibited during an indeterminate period of data in the color table RAM (26) so that flicker caused by a transfer of data between the CPU (1) and the color table RAM (26) is prevented from being occurred on the display. In the color table RAM (26), one of the regions A and B is selected dependent on a content of the VD8 bit, and one of blocks is selected dependent on a content of the VD4 to VD7 bits in the selected region A or B. In the selected block, one of addresses is accessed dependent on a content of the VD0 to VD3 bit. When color data are latched in the third flip-flop (27b), analog RGB signals and a composite signal can be produced as described before.



 
  
[Figure 8A/B] [Figures 8A and 8B] are a block diagram showing an apparatus for producing video signals in the embodiment and a timing chart in operation.
  
[Figure 8A/B] [Figures 8A and 8B] are a block diagram showing an apparatus for producing video signals in the embodiment and a timing chart in operation.